In source-synchronous systems, it is conventional for the receiver to align a clock signal with the data using a phase interpolator that includes a delay-locked loop. In such systems, a phase detector in the delay-locked loop detects a phase difference between the clock signal and the data. A loop filter in the delay-locked loop filters the phase detector output to produce a control voltage that controls a delay applied by a delay line to the received clock signal. In response to the control voltage, the delay line adaptively delays the received clock to produce a delayed clock signal (which may also be denoted as an interpolated clock signal). The delaying of the received clock signal to form the delayed clock signal keeps the delayed clock signal centered in the data eye for the received data so that the received data may be sampled accordingly by the delayed clock signal.
But the demands placed on the delay line are exacerbated as the data rates are pushed to greater and greater rates. At these higher data rates (which also correspond to an increased source-synchronous clock rate), the received clock signal may be out of phase with the received data signal by several clock periods. This phase difference between the received data signal and the received clock signal will vary with process, voltage, and temperature variations. A delay line for source-synchronous operation at high data rates (e.g., in excess of 10 GHz) typically requires a wide tuning range. But such a wide tuning range is directly correlated with increased power consumption, increased jitter, and increased phase noise. A reduced tuning range is conventionally preferred since such a tighter tuning range will reduce power consumption, jitter, and phase noise.
Accordingly, there is a need in the art for improved low-power source-synchronous systems having delay-locked loops offering a relatively wide tuning range while still providing reduced power consumption, jitter, and phase noise.